The present invention generally relates to video signal delay circuits, and more particularly to a video signal delay circuit at least comprising a semiconductor delay circuit part in which an input horizontal transfer register, a plurality of columns of vertical transfer registers and an output horizontal transfer register are arranged in a matrix arrangement. The video signal delay circuit according to the present invention delays an input composite video signal by a predetermined delay time, which predetermined delay time is variable.
Conventionally, in a video signal reproducing apparatus such as a video tape recorder (VTR), a delay circuit for providing a delay of one horizontal scanning period (1H) or one field is provided within a noise reduction circuit which reduces noise included within a reproduced composite video signal by use of the so-called line correlation or field correlation. A delay circuit is also often used for performing a dropout compensation. In other words, a delay circuit is conventionally used for various purposes.
In a conventional video signal delay circuit, an input composite video signal applied to an input terminal is delayed by a predetermined delay time in a semiconductor delay circuit part and is then produced through an output terminal after being passed through a lowpass filter wherein a frequency component of a horizontal transfer pulse is eliminated. The semiconductor delay circuit part comprises an input horizontal transfer register, an input vertical transfer gate, vertical transfer registers, an output vertical transfer gate, and an output horizontal transfer register. For example, as previously proposed in U.S. Pat. No. 4,536,795 entitled VIDEO MEMORY DEVICE, of which the assignee is the same as the assignee of the present application, the input horizontal transfer register, the vertical transfer registers and the output horizontal transfer register are constituted by cells of charge coupled devices (CCDs) which are arranged in a (n+1) row by m column matrix arrangement, where m and n are natural numbers. m cells in the first row of the matrix arrangement constitute the input horizontal transfer register. (n-1) xm cells in the second through n-th rows of the matrix arrangement constitute m columns of the vertical transfer registers. Further, m cells in the (n+1)-th row of the matrix arrangement constitute the output horizontal transfer register.
The input and output horizontal transfer registers are supplied with a horizontal transfer pulse which is generated based on a horizontal synchronizing signal within the input composite video signal. A data obtained by sampling the input composite video signal by the horizontal transfer pulse, is successively transferred horizontally within the input horizontal transfer register every time a horizontal transfer pulse is supplied thereto. m sampled data are supplied from the input horizontal transfer register to the vertical transfer registers in parallel through the input vertical transfer gate, and the m sampled data are successively transferred vertically within the respective vertical transfer registers at a rate of once for 1H responsive to a vertical transfer pulse which is generated based on a vertical synchronizing signal within the input composite video signal. Hence, the m sampled data stored in the input horizontal transfer register are supplied to the output horizontal transfer register after n vertical transfers in the vertical transfer registers. The m sampled data stored in the output horizontal transfer register are thereafter transferred horizontally responsive to the horizontal transfer pulse, so that the m sampled data are serially supplied to the lowpass filter. As a result, a composite video signal which is delayed by n horizontal scanning periods (nH) is obtained from the lowpass filter and is produced through the output terminal.
However, the conventional video signal delay circuit has a fixed delay time determined by the number of rows (number of stages which is (n-1) in the case described above) of the vertical transfer registers, and the delay time cannot be varied. Hence, a delay circuit for delaying the composite video signal by one field minus 1H (or one field plus 1H) cannot be used in common for the composite video signal employing 525 scanning lines and the composite video signal employing 625 scanning lines.
In addition, in a case where a signal processing is performed by use of the field correlation in the video signal, the conventional delay circuit can only provide a delay time which is a natural number multiple of 1H because there are a natural number of rows in the vertical transfer registers, although the number of scanning lines is equal to 262.5 for the system employing 525 scanning lines and 312.5 for the system employing 625 scanning lines and an odd number of 0.5 is introduced due to the interlaced scanning of the television video signal. Hence, the field correlation is deviated in the upward or downward direction of the picture, and an accurate field correlation does not exist.
Further, the conventional delay circuit cannot perform a horizontal transfer while a vertical transfer is being performed. Thus, there is a problem in that a signal in a time period corresponding to a time period in which the vertical transfer is performed, does not exist in the delayed composite video signal produced from the delay circuit.